1. Field of the Invention
The present invention relates generally to integrated circuit device design, and in particular to integrated circuit design techniques to mitigate on-chip noise of such device. More particularly, the present invention is directed to applying multiple voltage droop detection and instruction throttling instances with customized thresholds across semiconductor chips.
2. Description of the Related Art
Improvements in manufacturing processes are enabling integrated circuit devices to offer more functionality as the size of individual transistors contained therein get smaller and smaller, thus allowing more transistors to be packaged within an integrated circuit device. As the trend of integrating more functions in a single high performance integrated circuit device (also called a chip) continues, the on-chip noise condition due to switching activity on the chip has become a major new challenge. Power supply and power distribution system noise, especially voltage dips (droops) due to large step current increases, are a limiting factor in how fast the circuits in the processors can operate. Traditionally, decoupling capacitors have been used to limit the magnitude of this noise. However, as design frequencies have risen over the years, decoupling capacitance is becoming either less effective at the frequencies that are required to have an effect, or are too costly in financial terms or power dissipation terms.
U.S. patent application Ser. No. 11/420,825, entitled “Method For Detecting Noise Events In Systems With Time Variable Operating Points”, filed on May 30, 2006, and U.S. patent application Ser. No. 11/420,820, entitled “Mitigate Power Supply Noise Response By Throttling Execution Units Based Upon Voltage Sensing”, also filed on May 30, 2006, describe mechanisms that detect or sense the need to throttle power consuming executions in microprocessors that, because of the resulting step current change presented to the power distribution network, would result in voltage droops which may put circuits as risk of falling outside their operational limits. A voltage droop is a loss or dip in output voltage from a device as the device tries to drive a load. These patent applications are particularly applicable to optimize the power, performance, yield, added capacitance, and other parameters of a microprocessor when the microprocessor (and other integrated circuits) experiences common sensitivities to voltage fluctuations, and those fluctuations are coincident across all circuits.
However, there are situations where the sensitivity to voltage droop of circuits in any given location on the chip may be greater or less than those in other areas of the chip. These sensitivities to voltage droop fluctuations across the chip may be due to the process variations in the manufacturing of any particular chip, the temperature gradient in the application of the chip, the voltage gradient in the application, and/or the nature of the circuits themselves.